module WRAP_SDP36K_72_72(
   CLKA,
   WEA,
   ADDRA,
   DINA,
   CLKB,
   ADDRB,
   DOUTB
   );

input                 CLKA;
input                 WEA;
input[7:0]            ADDRA;
input[71:0]           DINA;
input                 CLKB;
input[7:0]            ADDRB;
output[71:0]          DOUTB;

wire[0:0]             wea_vector;

assign wea_vector[0]=WEA;


XILINX_V6_SDP36K_72_72  INST_XILINX_V6_SDP36K_72_72(
    .clka            ( CLKA ),
    .wea             ( wea_vector[0:0] ),
    .addra           ( ADDRA[7:0] ),
    .dina            ( DINA[71:0] ),
    .clkb            ( CLKB ),
    .addrb           ( ADDRB[7:0] ),
    .doutb           ( DOUTB[71:0] )
    );

endmodule
